Background and activities
I'm a PhD candidate (started mid-2013) with focus on computer architecture for accelerators at the Computing group, under the supervision of Magnus Jahre. Between Feb - Jul 2016 I was on leave from NTNU at Xilinx Research Labs Ireland.
- PhD (Computer Architecture), NTNU, 2013 - present
- MSc (European Master in Embedded Computing Systems), NTNU (Norway) and University of Southampton (UK), 2011 - 2013
- BSc (Computer Engineering), Middle East Technical University (Turkey), 2006 - 2011
My academic interests are heterogeneous architectures, machine learning and energy efficiency via application- or domain-specific accelerators. As part of the EECS (Energy Efficient Computing Systems) strategic research area, my current research focus is exploring how sparse and dense linear algebra maps to reconfigurable logic (FPGAs) with high performance and energy efficiency, in particular:
- accelerating irregular applications (e.g. sparse matrix multiplication and sparse graph exploration) with customized memory systems and caches
- accelerating deep learning inference with extreme quantization (e.g. binarized neural networks)
I am also interested in ease-of-programmability for heterogeneous architectures, programming models an abstractions for accelerating algorithms, system software and energy-efficient embedded systems.
A list of my publications can be found below, or in my Google Scholar profile. Additionally, the following papers are in press:
- Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers, "FINN: A Framework for Fast, Scalable Binarized Neural Network Inference", to appear in FPGA'17
- Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers, "Scaling Binarized Neural Networks on Reconfigurable Logic", to appear in PARMA-DITAM at HiPEAC'17
Teaching and Supervision
I am a teaching assistant for the following courses:
I have also supervised or co-supervised the following MSc theses:
- Turbo Amber: A high-performance processor core for the SHMAC, Andres T. Akre and Sebastian Bøe, 2014
- Hardware Acceleration of Convolutional Neural Networks, Magnus Halvorsen, 2015
- Bitcoin Mining on SHMAC, Kristian K. Skordal and Torbjørn Langland, 2015
Scientific, academic and artistic work
Displaying a selection of activities. See all publications in the database
- (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.
- (2015) Tre måneder på å gjøre det umulige. Gemini.
Part of book/report
- (2015) A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. Applied Reconfigurable Computing.
- (2015) Hybrid Breadth-First Search on a Single-Chip FPGA-CPU Heterogeneous Platform. 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015.
- (2014) An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators. 2014 32nd IEEE International Conference on Computer Design (ICCD).
- (2014) Memory-Centric Design for FPGA SpMV Accelerators. International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems . HiPEAC; Fiuggi. 2014-07-13 - 2014-07-19.