Background and activities
- PhD (Computer Architecture), NTNU, 2013 - present
- MSc (European Master in Embedded Computing Systems), NTNU and University of Southampton, 2011 - 2013
- BSc (Computer Engineering), Middle East Technical University, 2006 - 2011
Teaching and Supervision
I am a teaching assistant for the following courses:
I have also supervised or co-supervised the following MSc theses:
- Turbo Amber: A high-performance processor core for the SHMAC, by Andres T. Akre and Sebastian Bøe, 2014
My academic interests are heterogeneous architectures, energy efficiency via application- or domain-specific accelerators. My current research focus is accelerating irregular applications using reconfigurable logic to achieve high performance and energy efficiency. I also work with the SHMAC (Single-ISA Heterogeneous Manycore Computer) project as part of the EECS (Energy Efficient Computing Systems) strategic research area.
I am also interested in ease-of-programmability for heterogeneous architectures, programming models an abstractions for accelerating algorithms, system software and energy-efficient embedded systems.
A list of my publications can be found below, or in my Google Scholar profile. Additionally, the following papers are in press:
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators; Yaman Umuroglu and Magnus Jahre, to appear in Proceedings of the Int. Symp. in Applied Reconfigurable Computing 2015
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
Part of book/report
- (2014) An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators. 2014 32nd IEEE International Conference on Computer Design (ICCD).
- (2014) Memory-Centric Design for FPGA SpMV Accelerators. ACACES 2014: poster abstracts.