The Single-ISA Heterogeneous MAny-core Computer (SHMAC)

The Single-ISA Heterogeneous MAny-core Computer (SHMAC) is a research project initiated by EECS that aims to investigate the challenges posed by heterogeneous computing systems. Heterogeneous computing systems are likely because of the Dark Silicon effect. Dark Silicon is a result of the trend that we can still scale the transistor size, but that the transistor power consumption does not scales poorly. Consequently, we are left with an abundance of transistor resources where only a subset can be powered on simultaneously.

The Dark Silicon effect can be mitigated by two main strategies. First, multi-core architectures can be madeheterogeneous by including processing elements capable of general computation that have different performance and power characteristics. The task at hand is to select the processing elements that will maximize performance for the current application under a fixed power budget (i.e. maximizing energy efficiency). The remaining processing elements are powered off. Second, architects can add processing elements that are not capable of general computation but very energy efficient for their task. If this task does not occur, the unit is turned off. This technique is often referred to as specialization and the specialized unit is called an accelerator.

SHMAC High-level Architecture

The above figure illustrates the high level architecture of SHMAC processors. SHMAC is a tile-based architecture. In a tile-based architecture, processing elements are laid out in a rectangular grid with connections to their nearest neighbor. We identify each tile by its position in the grid on the form (n,m) where n gives the row and m gives the column. SHMAC uses a mesh interconnect which means that a middle tile (e.g. (1,1)) will have connections to its north, east, south and west neighbors. A border tile (e.g. (0,0)) will only have connections in the directions where there are neighbors.SHMAC supports heterogeneity by adding different tile types. The only requirement for a tile is that it implements SHMACs router interface.