Course - Nanoscale CMOS - FE8116
Nanoscale CMOS
Lessons are not given in the academic year 2011/2012
About
About the course
Course content
This course will be taught every second year, starting in Spring 2009. The course gives an introduction to the challenges associated with the scaling of CMOS electronics down to feature sizes of less than 100 nm. This scaling of critical dimensions in integrated electronics has followed an exponential trend for almost 40 years (Moor's law) and has resulted in a commensurable increase in performance and reduction in cost per function, which have laid the foundation for the remarkable progress in computer technology, communication and consumer electronics. In the present course, many of the technological challenges associated with this development are discussed. An important resource for insight into these problems is the International Technology Roadmap for Semiconductors (ITRS). The syllabus includes material from the latest updates of ITRS in addition to relevant, recent publications.
Learning outcome
Knowledge: The course gives insight into the technological challenges associated with the rapid down-scaling of CMOS-electronics.
Skills: Fundamental insight into advantages and limitations encountered by CMOS scaling into the nanometer range, and also insight into the physical modeling of such devices.
General competence: Insight into trends in the development of CMOS devices and circuits.
Learning methods and activities
Lectures. Exercises. Oral exam
Recommended previous knowledge
TFE4100 Electric circuits or equivalent
Required previous knowledge
None
Course materials
International Technology Roadmap for Semiconductors (ITRS), 2007 or later edition, (see: http://public.itrs.net/).
Relevant journal articles.
Subject areas
- Electronics
- Physical Electronics
- Technological subjects