Background and activities
Even is currently a PhD student in electrical engineering, low power CMOS-design. His main work tasks are:
1. To identify promising 1-bit memory cells suitable for the The Single-ISA Heterogeneous MAny-core Computer(SHMAC) platform.
2. To design and implement silicon prototypes, characterize the memory cells through laboratory measurements.
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2018) A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology. Integration. vol. 63.
- (2017) Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems. vol. 48.
- (2017) Ultra-Low Voltage and Energy Efficient Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Microprocessors and microsystems. vol. 56.
Part of book/report
- (2016) Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Proceedings of the 2nd IEEE Nordic Circuits and Systems Conference (NORCaS), 2016.
- (2015) Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015.