FE8119 - Modelling Theory for System on Chip and Embedded Systems


This course is no longer taught and is only available for examination. For a complete course description, see previous academic years.

Examination arrangement

Examination arrangement: Oral examination
Grade: Passed/Failed

Evaluation Weighting Duration Grade deviation Examination aids
Oral examination 100/100 D

Course content

Design methodology and system models, models for behaviour, finite state machines (FSM) and concurrency, models of time, process models, synchronous model assumption, models for communication, event based models, model domain interfaces, process networks, non-determinism and probability.

Learning outcome

A: Knowledge:

1 - The student shall have a deep understanding of the advanced theoretical models which are the logical and computational basis for descriptions of systems on chip (SoC) and embedded systems.

2 - The student shall understand how such advanced models are combined and used in terms of relevant applications within areas such as specification, simulation, verification, and synthesis.

B Skills:

1 - The student shall be able to analyse and develop models for system level descriptions and the necessary abstractions and principles therein for the specification, simulation, verification, and synthesis of systems on chip (SoC) and embedded systems.

Learning methods and activities

Colloquium, self study, term assignment

Required previous knowledge

Knowledge of hardware description languages such as VHDL, Verilog, and SystemC and the development of hardware based on such. Knowledge of simulation based verification of hardware.

Course materials

Axel Jantsch: "Modeling Embedded Systems and SOC's" (Morgan Kaufmann/Elsevier Science, 2004, 351 pages) Selected articles.

More on the course



Version: 1
Credits:  7.5 SP
Study level: Doctoral degree level


Language of instruction: English, Norwegian

Location: Trondheim

Subject area(s)
  • Electronics
  • Electrical Power Engineering
  • Technological subjects
Contact information
Course coordinator:

Department with academic responsibility
Department of Electronic Systems


Examination arrangement: Oral examination

Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
Autumn ORD Oral examination 100/100 D
Room Building Number of candidates
Spring ORD Oral examination 100/100 D
Room Building Number of candidates
  • * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.

For more information regarding registration for examination and examination procedures, see "Innsida - Exams"

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