Background and activities
Research interests: Computer architecture, parallel processing, multi- and many-core architectures and programming, chip multiprocessors and their memory systems, green computing, performance evaluation, energy-efficient computing and C++ programming.
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
Journal publications
- (2018) A vectorized k-means algorithm for compressed datasets: design and experimental analysis. Journal of Supercomputing. vol. 74 (6).
- (2017) Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study. Journal of Low Power Electronics and Applications. vol. 7 (1).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
- (2015) Tuning the victim selection policy of Intel TBB. Journal of systems architecture. vol. 61 (10).
- (2013) Performance and energy impact of parallelization and vectorization techniques in modern microprocessors. Computing.
- (2013) Performance and Power Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. Lecture Notes in Computer Science. vol. 7640.
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
- (2012) IPM based sparse LP solver on a heterogeneous processor. Computational Management Science. vol. 9.
- (2012) Case Studies of Multi-core Energy Efficiency in Task Based Programs. Lecture Notes in Computer Science. vol. 7453.
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Green Computing: Saving Energy by Throttling, Simplicity and Parallelization. UPGRADE : The European Journal for the Informatics Professional. vol. XII (4).
- (2010) Implementation of a Linear Programming Solver on the Cell BE Processor. Procedia Computer Science. vol. 1.
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.
- (2009) Towards an Intelligent Environment for Programming Multi-core Computing Systems. Lecture Notes in Computer Science. vol. 5415.
- (2009) A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Lecture Notes in Computer Science.
- (2009) A Compulsory Yet Motivating Question/Answer Game to Teach Computer Fundamentals. Computer applications in engineering education. vol. 17 (2).
- (2009) Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Transactions on Education. vol. 52 (1).
- (2007) An LRU-based Replacement Algorithm Augmented with Frequency of Access in Shared Chip-Multiprocessor Caches. SIGARCH Computer Architecture News.