Navigation

  • Skip to Content
NTNU Home

ntnu.edu

  • Studies
    • Master's programmes in English
    • For exchange students
    • PhD opportunities
    • All programmes of study
    • Courses
    • Financing
    • Language requirements
    • Application process
    • Academic calendar
    • FAQ
  • Research and innovation
    • NTNU research
    • Research excellence
    • Strategic research areas
    • Innovation resources
    • PhD opportunities
  • Life and housing
    • Student in Trondheim
    • Student in Gjøvik
    • Student in Ålesund
    • For researchers
    • Life and housing
  • About NTNU
    • Contact us
    • Faculties and departments
    • Libraries
    • International researcher support
    • Vacancies
    • About NTNU
    • Maps
  1. Home
  2. Employees

Språkvelger

Norsk

Rakesh Kumar

Rakesh Kumar

Associate Professor
Department of Computer Science
Faculty of Information Technology and Electrical Engineering

rakesh.kumar@ntnu.no
IT-bygget, 405, Gløshaugen, Sem Sælands vei 9, 7034 Trondheim
Publications Google Scholar
About Publications Media

About

CV

Rakesh Kumar is an Associate Professor in the Department of Computer Science at Norwegian University of Science and Technology (NTNU). He is affiliated with Computer Architecture Lab (CAL) in the Computing Unit. Before joining NTNU, he was a post-doctoral researcher at Uppsala University, Sweden and the University of Edinburgh, UK. He received his PhD from UPC, Barcelona in 2014.

Research

His current research focuses on improving the efficiency of large-scale datacenters through improvement in processor microarchitecture and memory systems. His previous work explored hardware/software co-designed processors (think of Nvidia Denver) as an energy-efficient alternative to conventional (hardware only) processors. He has also investigated dynamic code translation and optimizations, especially vectorization.

Teaching

  • TDT4258 Low Level Programming, Autumn 2021, 2020, 2019, 2018
  • TDT01 Architecture of Computing Systems, Autumn 2021, 2020, 2019, 2018
  • TFE4208 Embedded Systems Design Project, Spring 2022, 2021, 2020, 2019

Competencies

  • Computer architecture
  • Computer technology

Publications

  • Chronological
  • By category
  • See all publications in Cristin

2022

  • Asheim, Truls; Ahmed Khan, Tanvir; Kasikci, Baris; Kumar, Rakesh. (2022) Impact of Microarchitectural State Reuse on Serverless Functions. 8th International Workshop on Serverless Computing (WoSC).
    Academic chapter/article
  • Asheim, Truls; Grot, Boris; Kumar, Rakesh. (2022) A Specialized BTB Organization for Servers. The 31st International Conference on Parallel Architectures and Compilation Techniques (PACT).
    Academic chapter/article
  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2022) Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Transactions on Architecture and Code Optimization (TACO). volum 19 (2).
    Academic article
  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2022) Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. arXiv.org.
    Academic article
  • Kumar, Rakesh; Grot, Boris. (2022) Shooting Down the Server Front-End Bottleneck. ACM Transactions on Computer Systems. volum 38 (3-4).
    Academic article
  • Ugedal, Odin; Kumar, Rakesh. (2022) Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control. IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)..
    Academic chapter/article

2021

  • Ahmed Khan, Tanvir; Brown, Nathan; Sriraman, Akshitha; Soundararajan, Niranjan; Kumar, Rakesh; Devietti, Joseph; Subramoney, Sreenivas; Pokam, Gilles; Litz, Heiner; Kasikci, Baris. (2021) Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture.
    Academic chapter/article
  • Asheim, Truls; Grot, Boris; Kumar, Rakesh. (2021) BTB-X: A Storage-Effective BTB Organization. IEEE computer architecture letters. volum 20 (2).
    Academic article
  • Kumar, Rakesh; Martínez, Alejandro; Gonzalez, Antonio. (2021) A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors. arXiv.org.
    Academic article

2020

  • Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David. (2020) Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. IEEE Symposium on High-Performance Computer Architecture (HPCA).
    Academic article
  • Asheim, Truls; Kumar, Rakesh; Grot, Boris. (2020) Fetch-Directed Instruction Prefetching Revisited. arXiv.org.
    Academic article

2019

  • Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David. (2019) FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. Design, Automation and Test in Europe (DATE).
    Academic article
  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2019) Freeway: Maximizing MLP for Slice-Out-of-Order Execution. IEEE Symposium on High-Performance Computer Architecture (HPCA).
    Academic article

Scientific articles

  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2022) Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Transactions on Architecture and Code Optimization (TACO). volum 19 (2).
    Academic article
  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2022) Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. arXiv.org.
    Academic article
  • Kumar, Rakesh; Grot, Boris. (2022) Shooting Down the Server Front-End Bottleneck. ACM Transactions on Computer Systems. volum 38 (3-4).
    Academic article
  • Asheim, Truls; Grot, Boris; Kumar, Rakesh. (2021) BTB-X: A Storage-Effective BTB Organization. IEEE computer architecture letters. volum 20 (2).
    Academic article
  • Kumar, Rakesh; Martínez, Alejandro; Gonzalez, Antonio. (2021) A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors. arXiv.org.
    Academic article
  • Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David. (2020) Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. IEEE Symposium on High-Performance Computer Architecture (HPCA).
    Academic article
  • Asheim, Truls; Kumar, Rakesh; Grot, Boris. (2020) Fetch-Directed Instruction Prefetching Revisited. arXiv.org.
    Academic article
  • Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David. (2019) FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. Design, Automation and Test in Europe (DATE).
    Academic article
  • Kumar, Rakesh; Alipour, Mehdi; Black-Schaffer, David. (2019) Freeway: Maximizing MLP for Slice-Out-of-Order Execution. IEEE Symposium on High-Performance Computer Architecture (HPCA).
    Academic article

Part of book/report

  • Asheim, Truls; Ahmed Khan, Tanvir; Kasikci, Baris; Kumar, Rakesh. (2022) Impact of Microarchitectural State Reuse on Serverless Functions. 8th International Workshop on Serverless Computing (WoSC).
    Academic chapter/article
  • Asheim, Truls; Grot, Boris; Kumar, Rakesh. (2022) A Specialized BTB Organization for Servers. The 31st International Conference on Parallel Architectures and Compilation Techniques (PACT).
    Academic chapter/article
  • Ugedal, Odin; Kumar, Rakesh. (2022) Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control. IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)..
    Academic chapter/article
  • Ahmed Khan, Tanvir; Brown, Nathan; Sriraman, Akshitha; Soundararajan, Niranjan; Kumar, Rakesh; Devietti, Joseph; Subramoney, Sreenivas; Pokam, Gilles; Litz, Heiner; Kasikci, Baris. (2021) Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture.
    Academic chapter/article

Media

2020

  • Academic lecture
    Strupe, Fredrik; Kumar, Rakesh. (2020) Uncovering Hidden Instructions in Armv8-A Implementations. 9th International Workshop on Hardware and Architectural Support for Security and Privacy (HASP) ; 2020-10-17 - 2020-10-17.

2018

  • Poster
    Alipour, Mehdi; Kumar, Rakesh; Kaxiras, Stefanos; Black-Schaffer, David. (2018) A Minimum Out-of-Order Core. Student Research Competition at International Symposium on Microarchitecture (MICRO) . IEEE/ACM; 2018-10-20 - 2018-10-24.
NTNU
Studies
  • Master's programmes in English
  • For exchange students
  • PhD opportunities
  • Courses
  • Career development
  • Continuing education
  • Application process
Contact
  • Contact NTNU
  • Employees
  • For alumni
  • Press contacts
  • Researcher support
Discover NTNU
  • Experts
  • Vacancies
  • Pictures from NTNU
  • Innovation resources
  • NTNU in Gjøvik
  • NTNU in Trondheim
  • NTNU in Ålesund
  • Maps
About NTNU
  • NTNU's strategy
  • Research excellence
  • Strategic research areas
  • Organizational chart
  • Libraries
  • About the university
Services
  • For employees
  • For students
  • Blackboard
  • Intranet

Norwegian University of Science and Technology

Use of cookies
Accessibility statement (in Norwegian)
Privacy policy
Editoral responsibility
Sign In