FE8126 - Low-Voltage/Low-Power Analog CMOS

About

Examination arrangement

Examination arrangement: Oral examination
Grade: Passed/Failed

Evaluation form Weighting Duration Examination aids Grade deviation
Oral examination 100/100

Course content

Fundamental limits for low-voltage/low-power analog design, device modeling, biasing, design of amplifiers and other building blocks for low-voltage/low-power operation.

Learning outcome

Knowledge: The course aims to give knowledge on advanced techniques for design of low-voltage/low-power analog integrated circuits in CMOS technology. Skills: Design of low-voltage/low-power analog CMOS circuits with the aid of professional EDA tools.

Learning methods and activities

Lectures, colloquium, self-study. The course is part of the Norwegian PhD Network on Nanotechnology for Microsystems (www.nano-network.net). If students at other universities or university colleges sign up for the course, the teaching will be performed in 2-3 gatherings throughout the semester.

Course materials

Given at course start.

Credit reductions

Course code Reduction From To
FE8131 5.0 2011-09-01

Timetable

Detailed timetable

Examination

Examination arrangement: Oral examination

Term Statuskode Evaluation form Weighting Examination aids Date Time Room *
Autumn ORD Oral examination 100/100
Spring ORD Oral examination 100/100
  • * The location (room) for a written examination is published 3 days before examination date.
If more than one room is listed, you will find your room at Studentweb.