TDT4255 - Computer Design


Examination arrangement

Examination arrangement: School exam
Grade: Letter grades

Evaluation Weighting Duration Grade deviation Examination aids
School exam 100/100 4 hours D

Course content

Advanced topics in processor microarchitecture. Detailed discussion and implementation of simple pipelined CPUs. Introduction to the design and analysis of Instruction Set Architectures (ISAs). In-depth review of out-of-order execution, branch prediction, speculative execution, and performance modeling. Introduction to memory system design and performance modeling.

Learning outcome


  • The student should have a thorough understanding of the construction and mode of operation of pipelined processors.
  • The student should have a theoretical understanding of advanced performance improvement techniques for scalar processor cores including out-of-order execution, branch prediction, and speculative execution.
  • The student should have a basic understanding of analytical performance models for out-of-order processors.
  • The student should understand important trade-offs regarding instruction set design.
  • The student should have a basic understanding of memory system design.


  • The student should be able to implement optimised pipelined processors with a hardware description language.
  • The student should be able to evaluate computer architecture optimisations with a quantitative approach.

General competence:

  • The student should be proficient in computer design and be able to use this knowledge in projects at all levels of abstraction.

Learning methods and activities

Auditorium lectures, self-study. Compulsory laboratory exercises. Compulsory theory exercises. In-class problem solving. All teaching will be in English.

Compulsory assignments

  • Compulsory theoretical and practical exercises

Further on evaluation

All lectures are given in English. The written examination is only given in English.

The course contains a set of compulsory activities. The student can collect a fixed number of points in each activity and needs to collect a certain number of points in total to be allowed to take the exam. The list of activities and the scoring scheme will be announced at the start of the semester.

If there is a re-sit examination the examination form may change from written to oral.

Course materials

John L. Hennessy and David A. Patterson: "Computer Architecture - A Quantitative Approach, 6th Edition", Morgan Kaufmann Publishers. Other relevant texts will be announced at the start of the semester. All teaching materials will be in English.

Credit reductions

Course code Reduction From To
SIF8062 7.5

Version: 1
Credits:  7.5 SP
Study level: Second degree level


Term no.: 1
Teaching semester:  AUTUMN 2024

Language of instruction: English

Location: Trondheim

Subject area(s)
  • Informatics
  • Technological subjects
Contact information
Course coordinator:

Department with academic responsibility
Department of Computer Science


Examination arrangement: School exam

Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
Autumn ORD School exam 100/100 D INSPERA
Room Building Number of candidates
Summer UTS School exam 100/100 D INSPERA
Room Building Number of candidates
  • * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.

For more information regarding registration for examination and examination procedures, see "Innsida - Exams"

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