TFE4141 - Design of Digital Systems 1


Examination arrangement

Examination arrangement: Portfolio assessment
Grade: Letters

Evaluation form Weighting Duration Examination aids Grade deviation
Work 30/100
Written examination 70/100 4 hours A

Course content

The subject covers how complex digital circuits and systems are modelled and simulated using Hardware Describing Languages (HDL). We emphasize Register Transfer Level (RTL) descriptions adapted for correct synthesis to integrated circuits. Further we cover design-methods for effective test of digital circuits and systems. Labs and a semester project with FPGAs are included.

The subject covers these thematic parts:
Advanced use of HDL, automatic and manual synthesis of digital modules and components at RTL level. Realising digital circuits from standard components, programmable logic, and standard-cell based libraries, partitioning, placement and routing, integrated CAD/CAT systems, and trade-offs between performance, power consumption, and other functional and non-functional properties. Within test fault models, test-generation, fault simulation, design for testability, self-test, test quality and test standards are covered.

Learning outcome

A. Knowledge
The student shall
1. understand how advanced properties of Hardware Description Languages may be utilised to model digital circuits and systems.
2. understand how the functionality of digital circuits and systems may be verified using simulation and test-benches.
3. have knowledge about methods for high-level and register level synthesis of digital circuits and systems.
4. understand which design methods may be used to make digital components and systems testable.

B. Skills:
The student shall be able to
1. utilise state-of-the-art software to model digital circuits and systems using Hardware Description Languages.
2. write test-benches for simulation and verification of digital circuits and systems.
3. describe how synthesis tools optimizes and translates high-level and register-level hardware descriptions to digital circuits and systems.
4. design testable digital components and use software for such designs.

Learning methods and activities

Lectures. Practical/theoretical exercises, and a term project in groups of 2 students. All exercises are mandatory. The course will be given in English if any international students are registered.

Compulsory assignments

  • Exercises

Further on evaluation

Portfolio evaluation where the final exam counts for 70% and the term project 30%. Evaluation of each part is given as %-points. The evaluation of the complete portfolio is given as a grade letter.
If there is a re-sit examination, the examination form may be changed from written to oral.
If the exam is to be repeated, the whole course needs to be taken.

Specific conditions

Exam registration requires that class registration is approved in the same semester. Compulsory activities from previous semester may be approved by the department.

Required previous knowledge

Working knowledge of an HDL.

Course materials

Will be given at the semester start.

Credit reductions

Course code Reduction From To
FE8121 3.7 2014-09-01 2016-08-31
FE8128 3.7 2014-09-01 2016-08-31
TFE4140 3.7 2014-09-01
TFE4175 3.7 2014-09-01


Detailed timetable


Examination arrangement: Portfolio assessment

Term Statuskode Evaluation form Weighting Examination aids Date Time Room *
Autumn ORD Work 30/100
Autumn ORD Written examination 70/100 A 2017-12-20 09:00 R D1-185 Datasal , D1
  • * The location (room) for a written examination is published 3 days before examination date.
If more than one room is listed, you will find your room at Studentweb.