Course - Design of Digital Systems 1 - TFE4141
TFE4141 - Design of Digital Systems 1
About
Examination arrangement
Examination arrangement: Portfolio assessment
Grade: Passed/Failed
| Evaluation form | Weighting | Duration | Examination aids | Grade deviation |
|---|---|---|---|---|
| work | 30/100 | |||
| Home examination | 70/100 | 4 hours |
Course content
The subject covers how complex digital circuits and systems are modeled and simulated using Hardware Describing Languages (HDL). We emphasize on Register Transfer Level (RTL) descriptions adapted for correct synthesis to integrated circuits. Further we cover design-methods for effective test of digital circuits and systems. Labs and a semester project with FPGAs are included.
The subject covers these thematic parts:
Advanced use of HDL, automatic and manual synthesis of digital modules and components at RTL level. Realizing digital circuits from standard components, programmable logic, and standard-cell based libraries, partitioning, placement and routing, integrated CAD/CAT systems, and trade-offs between performance, power consumption, and other functional and non-functional properties. Within test fault models, test-generation, fault simulation, design for testability, self-test, test quality and test standards are covered.
Learning outcome
Knowledge
The candidate
-understands how advanced properties of Hardware Description Languages may be utilized to design (model) digital circuits and systems.
-understands how the functionality of digital circuits and systems may be verified using simulation and test-benches.
-has specialized knowledge about methods for high-level and register level synthesis of digital circuits and systems.
- has detailed understanding of design methods used to make digital components and systems testable.
B. Skills:
The candidate
-can use state-of-the-art software to model digital circuits and systems using Hardware Description Languages.
-can write test-benches for simulation and verification of digital circuits and systems.
-can use state-of-the-art synthesis tools to optimize and translate high-level and register-level hardware descriptions to digital circuits and systems.
-can design testable digital components and systems.
C. General competence:
The candidate
-can cooperate in a group on solving a practical project assignment.
-can present results from a project assignment in a project report.
Learning methods and activities
Lectures. Practical/theoretical exercises, and a term project in groups of 2 students. All exercises are mandatory. The course will be given in English if any international students are registered.
Compulsory assignments
- Exercises
Further on evaluation
Portfolio evaluation where the final exam counts for 70% and the term project 30%. Evaluation of each part is given as %-points. The evaluation of the complete portfolio is given as a grade letter. Individual evaluation of the term project can be given even if the project is performed in a group.
If there is a re-sit examination, the examination form may be changed from written to oral.
If the exam is to be repeated, the whole course needs to be taken.
Specific conditions
Exam registration requires that class registration is approved in the same semester. Compulsory activities from previous semester may be approved by the department.
Recommended previous knowledge
TFE4152 Design of Integrated Circuits or similar.
Required previous knowledge
Working knowledge of an HDL.
Course materials
Will be given at the semester start.
Credit reductions
| Course code | Reduction | From | To |
|---|---|---|---|
| TFE4140 | 3.7 | 01.09.2014 | |
| TFE4175 | 3.7 | 01.09.2014 |
No
Version: 1
Credits:
7.5 SP
Study level: Second degree level
Term no.: 1
Teaching semester: AUTUMN 2020
No.of lecture hours: 3
Lab hours: 4
No.of specialization hours: 5
Language of instruction: English, Norwegian
Location: Trondheim
- Electronics
- Electronics and Telecommunications
- Computers
- Electrical Power Engineering
- Physical Electronics
- Technological subjects
Department with academic responsibility
Department of Electronic Systems
Phone:
Examination
Examination arrangement: Portfolio assessment
- Term Status code Evaluation form Weighting Examination aids Date Time Digital exam Room *
- Autumn ORD work 30/100
-
Room Building Number of candidates -
Autumn
ORD
Home examination
70/100
Release 2020-12-19
Submission 2020-12-19
Release 09:00
Submission 13:00
INSPERA -
Room Building Number of candidates - Summer UTS Home examination 70/100 INSPERA
-
Room Building Number of candidates
- * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.
For more information regarding registration for examination and examination procedures, see "Innsida - Exams"