Course - Design of Integrated Circuits - TFE4152
TFE4152 - Design of Integrated Circuits
About
Examination arrangement
Examination arrangement: Aggregate score
Grade: Letter grades
Evaluation | Weighting | Duration | Grade deviation | Examination aids |
---|---|---|---|---|
Term assignment | 30/100 | |||
School exam | 70/100 | 4 hours | D |
Course content
The curriculum include construction and functionality of integrated circuits implemented in modern CMOS technology. This includes basic analog building blocks and modeling using Spice simulators. Synchronous sequential circuits and general digital functions are also included. Hardware descriptive languages (HDL) are used for specification and simuation of digital circuits and systems. Topics include: The subject deals with MOS transistors and simple analog circuits. The emphasis is towards digital circuits and systems, though. Basic principles for construction are considered. It includes CMOS technology and the MOS transistor: Function and characteristic properties. Static and dynamic analysis of logical functions. Simplified layout. Simple digital modules and an introduction to CAD tools are also treated. Guest lecturers from the electronic industry. Mandatory project: Design and verification of a small analog/digital circuit.
Learning outcome
knowledge: The candidate should * have detailed knowledge about the functioning of MOSFET transistors and models for these, including small signal LF-models. * have detailed knowledge about analog building blocks like current mirrors, and basic amplifiers implemented in CMOS. * have knowledge about the functioning of general VLSI system components for combinatorial circuits, arithmetics and memory. * have an understanding about principles for clocking as well as aspects concerning system design for synchronous sequential circuits. * have an understanding of basic characteristics like power consumption, energy consumption, delay and noise margins for CMOS circuitry. * have detailed knowledge about Spice simulators and hardware descriptive languages (HDLs). B. Skills: The candidate * can explain principles behind operation of basic analog and digital circuit building blocks in CMOS. * can combine analog and digital functions in system. * can simulate and model analog and digital building blocks, as well as sequential circuits. General competence: * can cooperate in a group to solve a practical project. * can present results from his/her work in a written report.
Learning methods and activities
Lectures, self study, mandatory exercises, and project. A minimum of 4 out of 6 exercises must be approved for entrance to the exam.
Compulsory assignments
- Exercises
Further on evaluation
The exam counts 70 %, and the project report 30 %, towards the final grade.
At least 4 out of 6 exercises must be approved for entrance to the exam.
If there is a re-sit examination in August, the examination form may be changed from written to oral.
If the course is to be repeated a later year, the entire course has to be retaken.
Recommended previous knowledge
TTT4203 Introduction to analog and digital electronics, TDT4160 Computers and digital design, or similar.
Course materials
Will be announced at course start.
Credit reductions
Course code | Reduction | From | To |
---|---|---|---|
TFE4151 | 7.5 | AUTUMN 2014 |
No
Version: 1
Credits:
7.5 SP
Study level: Third-year courses, level III
Term no.: 1
Teaching semester: AUTUMN 2024
Language of instruction: English
Location: Trondheim
- Electronics
- Applied Electrical Engineering
- Electrical Power Engineering
- Physical Electronics
- Technological subjects
Department with academic responsibility
Department of Electronic Systems
Examination
Examination arrangement: Aggregate score
- Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
- Autumn ORD School exam 70/100 D 2024-11-28 15:00 INSPERA
-
Room Building Number of candidates SL111 brun sone Sluppenvegen 14 54 SL110 lilla sone Sluppenvegen 14 64 -
Autumn
ORD
Term assignment
30/100
Submission
2024-11-22
INSPERA
14:00 -
Room Building Number of candidates - Summer UTS School exam 70/100 D INSPERA
-
Room Building Number of candidates
- * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.
For more information regarding registration for examination and examination procedures, see "Innsida - Exams"