Snorre Aunet
Background and activities
Snorre Aunet is a Professor at the Department of Electronics and Telecommunications. He is a member of the Circuits and Systems Group. He received a degree in electronics engineering from Trondheim Technical College in 1987, the cand.scient degree in informatics from UiO in 1993, and the dr.Ing degree in physical electronics from NTNU in 2002.
Research Interests
- Ultra low voltage/low power mixed-signal integrated circuits and defect- and error- tolerant circuits and microarchitectures
Employment history
- Since 2011: professor at NTNU
- 2015-2016 Sabbatical at University of California, San Diego
- Worked with ASIC design at Nordic VLSI (now Nordic Semiconductor) from 1994 to 1997. Since 1997 he has held different positions at the University of Oslo, and the same at NTNU.
- Visiting researcher at the Circuits and Systems Group, University of Paderborn; Germany, 2004-2012
Board/Council Work
- 2015 Co-chair Technical Programme NORCaS
- 2015 Co-chair of ECCTD
- 2013 Program Co-chair of DDECS
- 2009 Co-chair IEEE Norchip conference
Dr. Aunet has been an expert evaluator for the EU commission and a consultant for integrated circuit companies.
Scientific, academic and artistic work
Displaying a selection of activities. See all publications in the database
Journal publications
- (2018) A loadless 6T SRAM cell for sub- & near- threshold operation implementedin 28 nm FD-SOI CMOS technology. Integration. vol. 63.
- (2018) An Ultra-Low Voltage and Low-Energy Level Shifter in 28 nm UTBB-FDSOI. IEEE Transactions on Circuits and Systems - II - Express Briefs. vol. 66 (6).
- (2017) Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems. vol. 48.
- (2017) Ultra-Low Voltage and Energy Efficient Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Microprocessors and microsystems. vol. 56.
- (2016) Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. vol. 63 (6).
- (2015) Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. vol. 62 (4).
Part of book/report
- (2016) Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Proceedings of the 2nd IEEE Nordic Circuits and Systems Conference (NORCaS), 2016.
Report/dissertation
- (2002) Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS. 2002. ISBN 82-471-5447-1. Doktor ingeniøravhandling 2002:52, Institutt for fysikalsk elektronikk.