Background and activities
Snorre Aunet is a Professor at the Department of Electronics and Telecommunications. He is a member of the Circuits and Systems Group. He received a degree in electronics engineering from Trondheim Technical College in 1987, the cand.scient degree in informatics from UiO in 1993, and the dr.Ing degree in physical electronics from NTNU in 2002.
- Ultra low voltage/low power mixed-signal integrated circuits and defect- and error- tolerant circuits and microarchitectures
- Since 2011: professor at NTNU
- 2015-2016 Sabbatical at University of California, San Diego
- Worked with ASIC design at Nordic VLSI (now Nordic Semiconductor) from 1994 to 1997. Since 1997 he has held different positions at the University of Oslo, and the same at NTNU.
- Visiting researcher at the Circuits and Systems Group, University of Paderborn; Germany, 2004-2012
- 2015 Co-chair Technical Programme NORCaS
- 2015 Co-chair of ECCTD
- 2013 Program Co-chair of DDECS
- 2009 Co-chair IEEE Norchip conference
Dr. Aunet has been an expert evaluator for the EU commission and a consultant for integrated circuit companies.
Scientific, academic and artistic work
Displaying a selection of activities. See all publications in the database
- (2017) Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. Microprocessors and microsystems. vol. 48.
- (2016) Heavy Ion Characterization of Temporal-, Dual- and Triple Redundant Flip-Flops Across a Wide Supply Voltage Range in a 65 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. vol. 63 (6).
- (2015) Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process. IEEE Transactions on Nuclear Science. vol. 62 (4).
- (2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015. IEEE conference proceedings. 2015. ISBN 978-1-4673-6576-5.
Part of book/report
- (2016) Ultra-Low Voltage Adders in 28 nm FDSOI Exploring Poly-Biasing for Device Sizing. Proceedings of the 2nd IEEE Nordic Circuits and Systems Conference (NORCaS), 2016.
- (2016) 28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. Proceedings of the 23rd International Conference - "Mixed Design of Integrated Circuits and Systems" (MIXDES), Lodz, Poland.
- (2015) An Ultra-Low-Power/High-Speed 9-bit Adder Design: Analysis and Comparison Vs. Technology from 130nm-LP to UTBBFD-SOI-28nm. Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015.
- (2015) Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28nm FDSOI. Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015.
- (2015) 4 Sub-/Near-Threshold Flip-Flops with Application to Frequency Dividers. Proceedings, 2015 European Conference on Circuit Theory and Design.
- (2015) Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS. Proceedings of the 6th Asia Symposium on Quality Electronic Design.
- (2015) Exploiting Short Channel Effects and Multi-Vt Technology for Increased Robustness and Reduced Energy Consumption, with Application to a 16-bit Subthreshold Adder Implemented in 65 nm CMOS. Proceedings, 2015 European Conference on Circuit Theory and Design.