course-details-portlet

TFE4171 - Design of Digital Systems 2

About

Examination arrangement

Examination arrangement: Aggregate score
Grade: Letter grades

Evaluation Weighting Duration Grade deviation Examination aids
Project 20/100
School exam 60/100 4 hours C
Laboratory reports 20/100

Course content

This course deals with the challenges when developing complex digital systems such as a System-on-Chip (SoC). Focus is on advanced methods, notations and languages, tools and systems, high level (abstract) description and communication, simulation, and verification including UVM (Universal Verification Methodology). Verification will receive the highest focus.

Subjects are System On Chip as definition and the challenges in developing such, and also the system decription languages used for that purpose. For verification, both high level description and assertion based verification in SystemVerilog and UVM, and also formal verification with model checking is used.

Term project: The use of high level design tools for description, simulation, verification and implementation.

Learning outcome

Knowledge: The candidate has

  • detailed understanding of what characterizes systems-on-chip, how such are specified, designed, implemented and used, and what challenges lies within this.
  • advanced knowledge about high level descriptions of complex systems containing both hardware and software.
  • profound understanding of the principles in formal and assertion based verification.
  • detailed knowledge about the fundamentals and methods for modelling and simulation on system and transaction level.

Skills: The candidate can

  • use high level description languages for the design of modules for systems-on-chip or other complex system of hardware and software.
  • develop assertion based properties and use such for system level verification.
  • describe temporal logic system requirements and prove or disprove such by model checking.

Learning methods and activities

Lectures. Practical/theoretical exercises, and a term project in groups of 2 students. All laboratory exercises are mandatory.

Compulsory assignments

  • Laboratory exercises

Further on evaluation

If there is a re-sit examination, the examination form may be changed from written to oral. If the exam is to be repeated a later year, the laboratory exercises and the term project will be accepted up to three years after they have been approved.

Specific conditions

Compulsory activities from previous semester may be approved by the department.

Required previous knowledge

The student needs to know and be able to use at least one hardware description language such as VHDL or Verilog for register level modeling.

Course materials

Will be announced at course start.

Credit reductions

Course code Reduction From To
TFE4170 7.5 AUTUMN 2014
FE8129 7.5 AUTUMN 2014
TFE4175 3.7 AUTUMN 2014
FE8803 3.7 AUTUMN 2014
FE8128 3.7 AUTUMN 2014
SIE4075 3.7 AUTUMN 2014
More on the course

No

Facts

Version: 1
Credits:  7.5 SP
Study level: Second degree level

Coursework

Term no.: 1
Teaching semester:  SPRING 2023

Language of instruction: English

Location: Trondheim

Subject area(s)
  • Electronics
  • Applied Electrical Engineering
  • Electrical Power Engineering
  • Technological subjects
Contact information
Course coordinator: Lecturer(s):

Department with academic responsibility
Department of Electronic Systems

Examination

Examination arrangement: Aggregate score

Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
Spring ORD School exam 60/100 C
Room Building Number of candidates
Spring ORD Project 20/100 INSPERA
Room Building Number of candidates
Spring ORD Laboratory reports 20/100 INSPERA
Room Building Number of candidates
Summer UTS School exam 60/100 C
Room Building Number of candidates
  • * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.
Examination

For more information regarding registration for examination and examination procedures, see "Innsida - Exams"

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