course-details-portlet

TFE4187

Analog CMOS 1

Credits 7.5
Level Second degree level
Course start Autumn 2025
Duration 1 semester
Language of instruction English
Location Trondheim
Examination arrangement School exam

About

About the course

Course content

Frequency response, amplifier topologies, feedback, noise analysis, opertaional amplifiers, comparators, sample-and-hold circuits. Use of the SPICE simulation program.

Learning outcome

The course aims to provide a thorough understanding of design of analog integrated circuits in CMOS and an overview of fundamental building blocks in analog CMOS.

Knowledge: The candidate has - in depth understanding of the theoretical framework for design of analog integrated circuits - in-depth understand techniques used for sustainable design of analog CMOS integrated circuits - detailed knowledge of professional software tools used for design of analog CMOS circuits

Skills: The candidate can - combine earlier acquired knowledge and skills in math and electronics together with new theory to solve practical challenges in design of analog CMOS circuits - use professional software tools for design and simulation of analog CMOS circuits - design analog CMOS circuits

General competence: - present the results of the design project

Learning methods and activities

Lectures. Assignments, both theoretical and computer based. Mandatory term project and assignments.

Compulsory assignments

  • Exercises

Further on evaluation

Written exam only given in English. If there is a re-sit examination, in August, the examination form may be changed from written to oral.

Course materials

Announced at course start.

Credit reductions

Course code Reduction From
TFE4200 7.5 sp Autumn 2012
This course has academic overlap with the course in the table above. If you take overlapping courses, you will receive a credit reduction in the course where you have the lowest grade. If the grades are the same, the reduction will be applied to the course completed most recently.

Subject areas

  • Technological subjects

Contact information

Course coordinator

Department with academic responsibility

Department of Electronic Systems

Examination

Examination

Examination arrangement: School exam
Grade: Letter grades

Ordinary examination - Autumn 2025

School exam
Weighting 100/100 Examination aids Code D Date 2025-12-13 Time 09:00 Duration 4 hours Exam system Inspera Assessment
Place and room for school exam

The specified room can be changed and the final location will be ready no later than 3 days before the exam. You can find your room location on Studentweb.

Sluppenvegen 14
Room SL311 orange sone
4 candidates
Room SL110 turkis sone
20 candidates

Re-sit examination - Summer 2026

School exam
Weighting 100/100 Examination aids Code D Duration 4 hours Exam system Inspera Assessment Place and room Not specified yet.