Background and activities
Teaching
I am involved in teaching the following courses:
- TDT4255 Computer Design
- TDT4295 Computer Design Project (course wiki)
- DT8105 Computer Architecture 2
I also supervise project and master thesis topics within computer architecture and design. Current project and master thesis topics are available at IDIs web pages. I often co-supervise projects and masters with local and national industry partners such as ARM, Nordic Semiconductor and Silicon Labs (formerly Energy Micro).
The topics and reports of my supervised master theses can be found on NTNU Open.
Research
My main research area is memory systems for Chip Multiprocessors (CMPs). CMPs are often referred to as multi-core architectures. In addition, I am interested in heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software.
I am currently involved in the following research projects:
- Work Package leader in the EU Horizon 2020 project Towards Ubiquitous Low-power Image Processing Platforms (TULIPP)
- Principal investigator in the EU Horizon 2020 project Run-time Exploitation of Application Dynamism for Energy-efficient Exascale computing (READEX)
- Project Manager and PI for the Energy efficient high Performance computing research InfrastruCture (EPIC) project
- Principal investigator for the Reducing Power Consumption in Microprocessors (RPCM) project with Trondheim SME MyWo AS
- Project manager for the Single-ISA Heterogeneous MAny-core Computer (SHMAC) project
- Vectorized PARSEC Benchmarks (ParVec)
I currently supervise/mentor the following PhD students and post docs:
- Nico Reissmann (main supervisor)
- Dr. Asbjørn Djupdal (mentor)
- Benjamin Bjørnseth (co-supervisor)
- Even Låte (co-supervisor)
- Lahiru Rasnayake (co-supervisor)
- Mostafa Koraei (guest researcher)
I have supervised/metored the following PhD students and post docs:
- Main supervisor for Dr. Yaman Umuroglu (2012-2018), next employer Xilinx
- Co-supervisor for Dr. Yahya Yassin (2012-2018), next employer Mode Sensors
- Mentor for Dr. Ananya Muddukrishna (2016-2018), next employer ÅF
- Mentor for Dr. Mohammed Sourori (2015-2017), next employer Accenture
- Co-supervisor for Dr. Odd Rune Strømmen Lykkebø (2012-2017), next employer Nnaisense
- Mentor for Post doc. Dr. Juan Manuel Cebrian (2012-2014), next employer UPC/BSC
- Mentor for Post doc. Dr. Nikita Nikitin (2013-2014), next employer Mentor Graphics
- Informal co-supervisor for Dr. Alexandru Ciprian Iordan (2008-2017), next employer ARM
My most recent research appears below. For more details regarding my publications, visit my Google Scholar profile or Cristin.
The following papers are in press:
- Yuxi Liu, Xia Zhao, Magnus Jahre, Zhenlin Wang, Xiaolin Wang, Yingwei Luo and Lieven Eeckhout, "Get Out of the Valley: Power-Efficient Address Mapping for GPUs", To appear in the International Symposium on Computer Architecture (ISCA), 2018
- Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne, Antonio Paolillo, Diana Goehringer and Magnus Jahre, "Supporting Utilities for Heterogeneous Embedded Image Processing Systems (STHEM): An Overview", To appear in the International Symposium on Applied Reconfigurable Computing (ARC), 2018
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
2018
- (2018) GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime. High-Performance Computer Architecture.
2017
- (2017) Extending OMPT to Support Grain Graphs. Lecture Notes in Computer Science. vol. 10468 LNCS.
- (2017) The READEX formalism for automatic tuning for energy efficiency. Computing. vol. 99 (8).
- (2017) Scaling Binarized Neural Networks on Reconfigurable Logic. Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms.
- (2017) DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART).
- (2017) FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.
- (2017) Work-in-Progress: Towards Efficient Quantized Neural Network Inference on Mobile Devices. 2017 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).
2016
- (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.
2015
- (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
- (2015) Tuning the victim selection policy of Intel TBB. Journal of systems architecture. vol. 61 (10).
2014
- (2014) A study of energy and locality effects using space-filling curves. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS).
2013
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
2011
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Computational computer architecture. META.
2010
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.