Background and activities
I am involved in teaching the following courses:
- TDT4255 Computer Design
- TDT4295 Computer Design Project (course wiki)
- DT8105 Computer Architecture 2
- TDT1 Architecture of Computing Systems
I also supervise project and master thesis topics within computer architecture and design. Current project and master thesis topics are available at IDIs web pages. I often co-supervise projects and masters with local and national industry partners such as ARM, Nordic Semiconductor and Silicon Labs (formerly Energy Micro).
The topics and reports of my supervised master theses can be found on NTNU Open.
My main research area is memory systems for Chip Multiprocessors (CMPs). CMPs are often referred to as multi-core architectures. In addition, I am interested in heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software.
I am currently involved in the following research projects:
- Work Package leader in the EU Horizon 2020 project Towards Ubiquitous Low-power Image Processing Platforms (TULIPP)
- Principal investigator in the EU Horizon 2020 project Run-time Exploitation of Application Dynamism for Energy-efficient Exascale computing (READEX)
- Project Manager and PI for the Energy efficient high Performance computing research InfrastruCture (EPIC) project
- Principal investigator for the Reducing Power Consumption in Microprocessors (RPCM) project with Trondheim SME MyWo AS
- Project manager for the Single-ISA Heterogeneous MAny-core Computer (SHMAC) project
- Vectorized PARSEC Benchmarks (ParVec)
I currently supervise/mentor the following PhD students and post docs:
- Nico Reissmann (main supervisor)
- Yaman Umuroglu (main supervisor)
- Dr. Ananya Muddukrishna (mentor)
- Dr. Mohammed Sourouri (mentor)
- Dr. Asbjørn Djupdal (mentor)
- Benjamin Bjørnseth (co-supervisor)
- Even Låte (co-supervisor)
- Lahiru Rasnayake (co-supervisor)
- Yahya Yassin (co-supervisor)
- Mostafa Koraei (guest researcher)
I have supervised/metored the following PhD students and post docs:
- Co-supervisor for Dr. Odd Rune Strømmen Lykkebø (2012-2017), first employer Nnaisense
- Mentor for Post doc. Dr. Juan Manuel Cebrian (2012-2014), first employer UPC/BSC
- Mentor for Post doc. Dr. Nikita Nikitin (2013-2014), first employer Mentor Graphics
- Informal co-supervisor for Dr. Alexandru Ciprian Iordan (2008-2017), first employer ARM
The following papers are in press:
- Mostafa Koraei, Magnus Jahre and S. Omid Fatemi, "Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications", To appear in the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), 2017
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2017) The READEX formalism for automatic tuning for energy efficiency. Computing.
- (2017) Scaling Binarized Neural Networks on Reconfigurable Logic. Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms.
- (2017) FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays.
- (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.
- (2016) TULIPP: Towards Ubiquitous Low-power Image Processing Platforms. IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS).
- (2016) Efficient control flow restructuring for GPUs. International Conference on High Performance Computing & Simulation (HPCS).
- (2016) Compiling with the Regionalized Value State Dependence Graph. Acaces 2016: poster abstract.
- (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
- (2015) Tuning the victim selection policy of Intel TBB. Journal of systems architecture. vol. 61 (10).
- (2015) Compiling with the Regionalized Value State Dependence Graph. Acaces 2015: poster abstracts.
- (2014) A study of energy and locality effects using space-filling curves. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS).
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Computational computer architecture. META.
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.
- (2009) A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Lecture Notes in Computer Science.
- (2009) Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Transactions on Education. vol. 52 (1).