Background and activities
I am involved in teaching the following courses:
- TDT4255 Computer Design
- TDT4295 Computer Design Project
- DT8105 Computer Architecture 2
I also supervise project and master thesis topics within computer architecture and design. Current project and master thesis topics are available at IDIs web pages. I often co-supervise projects and masters with local and national industry partners such as ARM, Nordic Semiconductor and Silicon Labs (formerly Energy Micro).
The topics and reports of my supervised master theses can be found on NTNU Open.
My main research area is memory systems for Chip Multiprocessors (CMPs). CMPs are often referred to as multi-core architectures. In addition, I am interested in heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software. I am currently serving as the deputy head of the Computing research group.
I am currently involved in the following research projects:
- Project Manager and PI of the Balancing Compute and Memory Performance in Reconfigurable Accelerators with Analytical Modeling (BAMPAM) project. BAMPAM is a young research talents project funded by the Norwegian Research Council program IKTPLUSS.
- PI in the Non-Intrusive Power Monitor for Low-Energy Computing Systems (NIPOLECS) project. NIPOLECS is funded by TETRAMAX.
- Scientific coordinator for the Energy efficient high Performance computing research InfrastruCture (EPIC) project
We recently completed the TULIPP Horizon 2020 project. One of the key outcomes of TULIPP was the definition of a reference platform for high-performance low-power embedded image processing. Another key contribution is the STHEM utilities which makes it possible to non-intrusively estabilsh the energy consumption of source code constructs such as procedures and loops [video]. To make full use of STHEM, you need the Lynsyn power measurement unit which can be bought from Sundance.
I currently supervise/mentor the following PhD students and post docs:
- Björn Gottschall (main supervisor)
- Benjamin Bjørnseth (co-supervisor)
- Even Låte (co-supervisor)
- Lahiru Rasnayake (co-supervisor)
- Mostafa Koraei (guest researcher)
I have supervised/metored the following PhD students and post docs:
- Main supervisor for Dr. Nico Reissmann (2012-2019), next employer NTNU IT
- Mentor for Dr. Asbjørn Djupdal (2013-2019), next employer NTNU
- Main supervisor for Dr. Yaman Umuroglu (2012-2018), next employer Xilinx
- Co-supervisor for Dr. Yahya Yassin (2012-2018), next employer Mode Sensors
- Mentor for Dr. Ananya Muddukrishna (2016-2018), next employer ÅF
- Mentor for Dr. Mohammed Sourori (2015-2017), next employer Accenture
- Co-supervisor for Dr. Odd Rune Strømmen Lykkebø (2012-2017), next employer Nnaisense
- Mentor for Post doc. Dr. Juan Manuel Cebrian (2012-2014), next employer UPC/BSC
- Mentor for Post doc. Dr. Nikita Nikitin (2013-2014), next employer Mentor Graphics
- Informal co-supervisor for Dr. Alexandru Ciprian Iordan (2008-2017), next employer ARM
The following papers are in press:
- Scalability Analysis of AVX-512 Extensions, Juan M. Cebrian, Lasse Natvig, and Magnus Jahre, to appear in Journal of Supercomputing
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2018) GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime. High-Performance Computer Architecture. vol. 2018-February.
- (2018) Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview. Lecture Notes in Computer Science. vol. 10824.
- (2018) Get Out of the Valley: Power-Efficient Address Mapping for GPUs. International Symposium on Computer Architecture.
- (2018) Developing Low-Power Image Processing Applications with the TULIPP Reference Platform Instance. Hardware Accelerators in Data Centers.
- (2017) Extending OMPT to Support Grain Graphs. Lecture Notes in Computer Science. vol. 10468 LNCS.
- (2017) The READEX formalism for automatic tuning for energy efficiency. Computing. vol. 99 (8).
- (2017) Scaling Binarized Neural Networks on Reconfigurable Logic. Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms.
- (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.
- (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
- (2015) Tuning the victim selection policy of Intel TBB. Journal of systems architecture. vol. 61 (10).
- (2014) A study of energy and locality effects using space-filling curves. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS).
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Computational computer architecture. META.
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.