Background and activities
I am involved in teaching the following courses:
I also supervise project and master thesis topics within computer architecture and design. Current project and master thesis topics are available at IDIs web pages. I often co-supervise projects and masters with local and national industry like ARM, Nordic Semiconductor and Silicon Labs (formerly Energy Micro).
The topics and reports of my supervised master theses can be found in DAIM.
My main research area is memory systems for Chip Multiprocessors (CMPs). CMPs are often referred to as multi-core architectures. In addition, I am interested in heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software.
I am currently involved in the following research projects:
- Coordinator and process leader of the Energy Efficient Computing Systems (EECS) initative. EECS is one of seven groups at NTNU that get special support towards Horizon 2020.
- Project manager for the Single-ISA Heterogeneous MAny-core Computer (SHMAC) project
- Vectorized PARSEC Benchmarks (ParVec)
I currently supervise/mentor the following PhD students and post docs:
- Nico Reissmann (main supervisor)
- Yaman Umuroglu (main supervisor)
- Dr. Asbjørn Djupdal (mentor)
- Benjamin Bjørnseth (co-supervisor)
- Odd Rune Strømmen Lykkebø (co-supervisor)
- Even Låte (co-supervisor)
- Yahya Yassin (co-supervisor)
I have supervised/metored the following PhD students and post docs:
- Post doc. Dr. Juan Manuel Cebrian (2012-2014)
- Post doc. Dr. Nikita Nikitin (2013-2014)
In addition, the following papers are currently in press:
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing.
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Computational computer architecture. META.
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.
- (2009) A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Lecture Notes in Computer Science.
- (2009) Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Transactions on Education. vol. 52 (1).
Part of book/report
- (2015) A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. Applied Reconfigurable Computing.
- (2014) Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks. IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.
- (2014) Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. Architecture of Computing Systems – ARCS 2014.
- (2014) Graph-based Performance Accounting for Chip Multiprocessor Memory Systems. Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT).
- (2014) Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis. 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14).
- (2014) A Study of Energy and Locality Effects using Space-filling Curves. Proceedings of the 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2014) and IPDPS 2014 Workshops (IPDPSW 2014).
- (2014) An Energy Efficient Column-Major Backend for FPGA SpMV Accelerators. 2014 32nd IEEE International Conference on Computer Design (ICCD).
- (2014) Memory-Centric Design for FPGA SpMV Accelerators. ACACES 2014: poster abstracts.
- (2013) On the Energy Footprint of Task Based Parallel Applications. Proceedings of the 2013 International Conference on High Performance Computing & Simulation (HPCS 2013).
- (2013) Energy Efficient Memory Systems. Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems.