Magnus JahreAssociate Professor Department of Computer and Information Science Faculty of Information Technology, Mathematics and Electrical Engineering
firstname.lastname@example.org +47 73593680 +47 95222309
Background and activities
I am involved in teaching the following courses:
- TDT4255 Computer Design
- TDT4295 Computer Design Project (course wiki, department presentation)
- DT8105 Computer Architecture 2
- TDT1 Architecture of Computing Systems
I also supervise project and master thesis topics within computer architecture and design. Current project and master thesis topics are available at IDIs web pages. I often co-supervise projects and masters with local and national industry partners such as ARM, Nordic Semiconductor and Silicon Labs (formerly Energy Micro).
The topics and reports of my supervised master theses can be found on NTNU Open.
My main research area is memory systems for Chip Multiprocessors (CMPs). CMPs are often referred to as multi-core architectures. In addition, I am interested in heterogeneous computer systems, energy efficiency, computer architecture simulation, compilers and system software.
I am currently involved in the following research projects:
- Work Package leader in the EU Horizon 2020 project Towards Ubiquitous Low-power Image Processing Platforms (TULIPP)
- Principal investigator in the EU Horizon 2020 project Run-time Exploitation of Application Dynamism for Energy-efficient Exascale computing (READEX)
- Coordinator and process leader of the Energy Efficient Computing Systems (EECS) initative. EECS is one of seven groups at NTNU that get special support towards Horizon 2020.
- Project manager for the Single-ISA Heterogeneous MAny-core Computer (SHMAC) project
- Vectorized PARSEC Benchmarks (ParVec)
I currently supervise/mentor the following PhD students and post docs:
- Nico Reissmann (main supervisor)
- Yaman Umuroglu (main supervisor)
- Dr. Ananya Muddukrishna (mentor)
- Dr. Mohammed Sourouri (mentor)
- Dr. Asbjørn Djupdal (mentor)
- Benjamin Bjørnseth (co-supervisor)
- Odd Rune Strømmen Lykkebø (co-supervisor)
- Even Låte (co-supervisor)
- Yahya Yassin (co-supervisor)
- Mostafa Koraei (guest researcher)
I have supervised/metored the following PhD students and post docs:
- Post doc. Dr. Juan Manuel Cebrian (2012-2014)
- Post doc. Dr. Nikita Nikitin (2013-2014)
The following papers are in press:
- Nico Reissmann, Thomas L. Falch, Benjamin A. Bjørnseth, Helge Bahmann, Jan Christian Meyer and Magnus Jahre, "Efficient Control Flow Restructuring for GPGPU Programs", to appear in the 2016 International Conference on High Performance Computing & Simulation (HPCS)
- Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre and Kees Vissers, "FINN: A Framework for Fast, Scalable Binarized Neural Network Inference", to appear in the 25th International Symposium on Field-Programmable Gate Arrays (FPGA2017)
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2016) Random access schemes for efficient FPGA SpMV acceleration. Microprocessors and microsystems. vol. 47B.
- (2015) Perfect Reconstructability of Control Flow from Demand Dependence Graphs. ACM Transactions on Architecture and Code Optimization (TACO). vol. 11 (4).
- (2015) ParVec: vectorizing the PARSEC benchmark suite. Computing. vol. 97 (11).
- (2015) Tuning the victim selection policy of Intel TBB. Journal of systems architecture. vol. 61 (10).
- (2015) Compiling with the Regionalized Value State Dependence Graph. Acaces 2015: poster abstracts.
- (2015) A Vector Caching Scheme for Streaming FPGA SpMV Accelerators. Applied Reconfigurable Computing.
- (2015) Hybrid Breadth-First Search on a Single-Chip FPGA-CPU Heterogeneous Platform. 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015.
- (2014) A study of energy and locality effects using space-filling curves. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS).
- (2014) Optimized Hardware for Suboptimal Software: The Case for SIMD-aware Benchmarks. IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE.
- (2014) Victim Selection Policies for Intel TBB: Overheads and Energy Footprint. Architecture of Computing Systems – ARCS 2014.
- (2014) Graph-based Performance Accounting for Chip Multiprocessor Memory Systems. Proceedings of the 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT).
- (2014) Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level Synthesis. 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'14).
- (2013) Challenges of Reducing Cycle-Accurate Simulation Time for TBP Applications. Procedia Computer Science. vol. 18.
- (2011) Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy. Lecture Notes in Computer Science. vol. 6566.
- (2011) Storage Efficient Hardware Prefetching using Delta-Correlating Prediction Tables. Journal of Instruction-Level Parallelism. vol. 13.
- (2011) Computational computer architecture. META.
- (2010) Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching. Lecture Notes in Computer Science. vol. 5 (1).
- (2010) DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems. Lecture Notes in Computer Science.
- (2009) A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. Lecture Notes in Computer Science.
- (2009) Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals. IEEE Transactions on Education. vol. 52 (1).