Per Gunnar Kjeldsberg
Background and activities
Per Gunnar Kjeldsberg was born in Trondheim, Norway in 1966. He received his Sivilingeniør degree (MSc) in electrical engineering in 1992 from the Norwegian Institute of Technology (NTH). In 2001 he received the degree of Doktor ingeniør (PhD) from the same institution (now Norwegian University of Science and Technology, NTNU). Between 1992 and 1996 he worked as a design engineer at the company Eidsvoll Electronics AS. Kjeldsberg is now Professor at Department of Electronic Systems, NTNU. His research interests are embedded heterogeneous multi-processor systems, with a focus on multi-media and digital signal processing applications. He has participated in several national and international research projects, among them several EU Horizon 2020 projects, being work package leader in the FET-HPC project READEX and principal researcher in the LEIT project Tulipp. Currently he is supervisor in the MSCA-IF project Palmera. Kjeldsberg is Senior Member of IEEE and member of HiPEAC, a European Network of Excellence on High Performance and Embedded Architecture and Compilation. At NTNU Kjeldsberg is group leader of the Circuit and Radio Systems group and project leader for a strategic research initiative on Energy Efficient Computing Systems. Throughout his career, Kjeldsberg has cooperated closely with imec, in Leuven, Belgium, where he has been visiting researcher for nine months in all. He has also been visiting researcher at University of California, Irvine, Center for Embedded Computer Systems, at imec Netherlands at the Holst Centre in Eindhoven, and at School of Computer Science and Engineering, University of New South Wales, Sydney, Australia. Kjeldsberg has published extensively at conferences and in journals, and has been coauthor of three books in his fields of interest. At NTNU he teaches both undergraduate and graduate courses, and supervises a number of students at master and PhD level. Kjeldsberg is and has been a member of the board of directors both at the Faculty and in private companies. He is frequently used as reviewer for several international journals and conferences.
My research intersts include energy efficient embedded systems and heterogeneous multi-processor systems, with a focus on Internet of Things (IoT), multi-media and digital signal processing applications.
I am or have recently been involved in the following major projects and groups:
Low Power and Fault Tolerant Cache Memory Design through a Combination of Hardware and Software Approaches (Palmera), a European Union Horizon 2020 Marie Sklodowska-Curie Individual Fellowships project (grant agreement No 799481).
Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing (READEX ), a European Union Horizon 2020 research and innovation project (grant agreement No 671657).
Towards Ubiquitous Low-power Image Processing Platforms (Tulipp), a European Union Horizon 2020 innovation project (grant agreement No 688403).
HiPEAC, European Network of Excellence on High Performance and Embedded Architecture and Compilation (grant agreement number 779656).
Energy Efficient Computing Systems (EECS), an inter-department Strategic Research Arena at NTNU.
Special-interest group on ''Scenario Driven Design for Embedded Systems'', a cooperation between several Europen universities.
A complete list of my publications can be found here.
Main Teaching Responsibilities
TFE4141 Design of Digital Systems 1: a master level course on modeling and analysis of digital systems.
TFE4208 Embedded Systems Design Project: a project based master level course on embedded systems design.
FE8109 - Design and Utilization of Memory Hierarchies in Multi-Media Applications: a PhD student course.
Dr.ing. (PhD, Electrical Engineering), Norwegian University of Science and Technology, March 2001. Thesis: Storage Requirement Estimation and Optimization for Data Intensive Applications.
Siv.ing. (MSc, Electrical Engineering), Norwegian Institute of Technology (now Norwegian University of Science and Technology), June 1992. Diploma thesis: Hurtig simulator for logiske kretser (in English: Fast Simulator for Synchronous Circuits).
Industrial work Experience
Between 1992 and 1996 I worked as a Design Engineer at Eidsvoll Electronics AS.
Married, having three daugthers and a labrador. Living at Byåsen in Trondheim. Currently living with family but without dog in Maroubra, Syndey, Australia (until July 2020).
Playing flute in Strinda ungdomskorps (wind band / marching band).
Cycling and cross country skiing (just to keep myself in shape).
Enjoy amateur theater, though not very active lately.
- TFE4580 - Electronic Systems Design and Innovation, Specialization Project
- TFE4590 - Electronic Systems Design, Specialization Project
- TFE4595 - Electronic Systems Design, Specialization Course
- TFE4141 - Design of Digital Systems 1
- TFE4208 - Embedded Systems Design Project
- FE8122 - PhD Seminar in Circuit and Radio Systems Design
Scientific, academic and artistic work
A selection of recent journal publications, artistic productions, books, including book and report excerpts. See all publications in the database
- (2022) Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications with High Reliability Requirements. IEEE Access. vol. 10.
- (2021) Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. Journal of Signal Processing Systems. vol. 93 (1).
- (2018) Runtime Precomputation of Data-Dependent Parameters in Embedded Systems. ACM Transactions on Embedded Computing Systems. vol. 17 (3).
- (2018) Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios. Microprocessors and microsystems. vol. 56.
- (2018) Algorithm/Architecture Co-optimisation Technique for Automatic Data Reduction of Wireless Read-Out in High-Density Electrode Arrays. ACM Transactions on Embedded Computing Systems. vol. 17 (3).
- (2017) Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study. Journal of Low Power Electronics and Applications. vol. 7 (1).
- (2017) The READEX formalism for automatic tuning for energy efficiency. Computing. vol. 99 (8).
- (2016) Integrated exploration methodology for data interleaving and data-to-memory mapping on SIMD architectures. ACM Transactions on Embedded Computing Systems. vol. 15 (3).
- (2014) Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios. Design automation for embedded systems.
- (2014) Realization of dynamical electronic systems. The European Physical Journal Conferences. vol. 70.
- (2013) Performance and Power Efficiency Analysis of Data Reuse Transformation Methodology on Multicore Processor. Lecture Notes in Computer Science (LNCS). vol. 7640.
- (2009) Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study. Lecture Notes in Computer Science (LNCS). vol. 5657.
- (2009) Power Optimization of Parallel Multipliers in Systems with Variable Word-length. Lecture Notes in Computer Science (LNCS). vol. 5349.
- (2008) Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications. Journal of Signal Processing Systems. vol. 53 (1-2).
- (2008) Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. Journal of Signal Processing Systems. vol. 53 (3).
- (2007) Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data. Lecture Notes in Computer Science (LNCS). vol. 4644.
- (2007) Incremental hierarchical memory size estimation for steering of loop transformations. ACM Transactions on Design Automation of Electronic Systems. vol. 12 (4).
- (2007) Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 26 (4).
- (2006) Destructive-Read in Embedded DRAM, Impact on Power Consumption. Journal of Embedded Computing.
- (2006) Polyhedral space generation and memory estimation from interface and memory models of real-time video systems. Journal of Systems and Software. vol. 79 (2).