Background and activities

Magnus Själander is an Associate Professor at the Department of Computer Science and a Visiting Senior Lecturer at the Department of Information Technology, Uppsala University. He is the coordinator of the Energy Efficient Computing Systems (EECS) research initiative at NTNU and the head of the Computing unit at the Department of Computer Science, NTNU. Själander has an M.Sc. from Luleå University, a Ph.D. from Chalmers University of Technology, and a Docent from Uppsala University. Before joining NTNU, Själander worked as a Digital Design Engineer at Aeroflex Gaisler (2008-2009) and as a researcher at NXP Semiconductors (2007), Florida State University (2012-2013), and Uppsala University (2014-2015).

Research

Själander's research focuses on the design of high-performance and energy-efficient systems at all scales. His background lies primarily in computer architecture and circuit design, and he has led implementation projects in both FPGA and ASIC technologies. Recent projects focus increasingly on hardware/software codesign and efficient low-power systems (compiler, architecture, and hardware implementation) for high-efficiency computing. The driving philosophy behind these projects is that by extracting more information from the application and by monitoring the system, we can better control the hardware to use resources more efficiently in terms of performance and power.

Groups

Projects

Teaching

Publications

See the Google Scholar profile.

List of VLSI Related Conferences.

List of Computer Architecture Related Conferences.

Selected Publications

Power Efficiency

M. Själander, M. Martonosi, and S. Kaxiras, "Power-Efficient Computer Architectures: Recent Advances", Synthesis Lectures on Computer Architecture, Morgan & Claypool, Dec. 2014. ISBN: 978-1-62705-645-8.

B. Goel, S. A. McKee, and M. Själander, "Techniques to Measurement, Model, and Manage Power",
Advances in Computers, Green and Sustainable Computing: Part I vol. 87, Nov. 2012. ISBN: 978-0-12-396528-8

Secure Speculative Execution

K.-A. Tran, C. Sakalis, M. Själander, A. Ros, S.Kaxiras, and A. Jimborean, "Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design", Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct. 2020.

C. Sakalis, S. Kaxiras, A. Ros, A. Jimborean, and M. Själander, "Understanding Selective Delay as a Method for Efficient Secure Speculative Execution", IEEE Transactions on Computers (TC), Aug. 2020.

C. Sakalis, S.Kaxiras, A. Ros, A. Jimborean, and M. Själander, "Efficient Invisible Speculative Execution through Selective Delay and Value Prediction", Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2019.

C. Sakalis, M. Alipour, A. Ros, A. Jimborean, S. Kaxiras, and M. Själander, "Ghost loads: what is the cost of invisible speculation?", Proceedings of the ACM International Conference on Computing Frontiers (CF), pp. 153-163, May 2019.

Bit-serial Matrix-matrix Multiplication

Y. Umuroglu, C. Davide, L. Rasnayake, T. B Preusser, and M. Själander, "Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 12, no. 3, pp. 1-24, Aug. 2019.

Y. Umuroglu, L. Rasnayake, and M. Själander, "BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing", Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2018.

Instruction Scheduling

K.-A. Tran, A. Jimborean, T. Carlson, K. Koukos, M. Själander, and S. Kaxiras, "SWOOP: Software-Hardware Co-Design for Non-Speculative, Execute-Ahead, In-Order Cores", Proceedings of the ACM International Conference on Programming Language Design and Implementation (PLDI), pp. 328-343, June 2018.

K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoilos, S. Kaxiras, and A. Jimborean, "Clairvoyance: Look-Ahead Compile-time Scheduling", Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp. 171-184, 4-8 Feb. 2017.

K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean, "Static Instruction Scheduling for High Performance on Limited Hardware", IEEE Transactions on Computers (TC), vol. 67, no. 4, pp. 513-527, Nov. 2017.

M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström, "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing", Journal of Signal Processing Systems, vol. 57, no. 1, pp. 5-19, Oct. 2009.

Task Scheduling

R. Nishtala, V. Petrucci, P. M. Carpenter, and M. Själander, "Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services", Proceedings of the ACM International Conference on High-Performance Computer Architecture (HPCA), Feb. 2020.

M. Själander, A. Terechko, M. Duranton, "A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures", Proceedings of Euromicro Conference on Digital System Design: Architectures, Methods, and Tools (DSD), pp. 149-157, 3-5 Sep. 2008.

Optimizing Compilers

N. Reissmann, J. C. Meyer, H. Bahmann, and M. Själander, "RVSDG: An Intermediate Representation for Optimizing Compilers", ACM Transactions on Embedded Computing Systems (TECS), Mar. 2020.

Cache Optimizations

A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors, "Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance", ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, pp. 54:1--54:25, Dec. 2013.

P. Gavin, D. Whalley, and M. Själander, "Reducing Instruction Fetch Energy in Multi-Issue Processors", ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, pp. 64:1--64:24, Dec. 2013.

A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors, "Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches", Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 302-308, 6-9 Oct. 2013.

Multiplier Design

M. Själander, and P. Larsson-Edefors, "Multiplication Acceleration through Twin Precision", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 17, no. 9, pp. 1233-1246, Sep. 2009.

H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, M. Schölin, "Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4-8, 21-24 May 2006.