PALMERA has received funding from the European Union’s Horizon 2020 research and innovation program under the Marie Sklodowska-Curie grant agreement No. 799481 and for a duration of two years (May 2019-May 2021). PALMERA investigates Low-Power and Fault-Tolerant Cache Memory Design Bottleneck through a Combination of Hardware and Software approaches.
- A. Seyedi, S. Aunet and P. G. Kjeldsberg, "Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements," in IEEE Access, vol. 10, pp. 30624-30642, 2022.
- A. Seyedi, S. Aunet and P. G. Kjeldsberg, "Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications," 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019, pp. 1-6.
- PALMERA presented a seminar at IDEAS on April 28, 2022.
- PALMERA presented a lecture to the Circuit and Radio Systems group on May 6, 2022.
- PALMERA published a paper in IEEE ACCESS 2022.
- PALMERA published a paper in NORCAS 2019.
- PALMERA will present a poster in HiPEAC booth @ DATE 2020 - Project Participation.
- PALMERA will present a seminar in Gemini PhD seminar on May 28, 2020.
- PALMERA will present a poster in ACASES 2020. An abstract will be published in the ACASES booklet as well.
- PALMERA presented a poster in a PhD day at the Department of Electronic Systems on April 26, 2019.
- PALMERA presented a lecture to the Circuit and Radio System group on November 29, 2019.
- PALMERA presented a seminar in Gemini PhD seminar June 20, 2018.